The present invention relates to a process of fabricating a semiconductor IC device, particularly a bipolar semiconductor IC device which is suitable for higher integration and higher operating speed.
Where high speed operations are required, bipolar semiconductor IC devices of ECL/CML (emitter coupled logic/current mode logic) are widely used.
Where the power consumption and the logic swing is fixed in ECL/CML circuits, the operating speed of the circuit is determined mainly by the base resistance r.sub.b and, the gain-bandwidth product f.sub.T of the transistors constituting the circuit, and the parasitic capacitances of the transistors, resistors and wiring conductors.
To reduce the parasitic capacitances, thick oxide is used for isolation between elements. To reduce the base-collector junction capacitance which has a great effect on the operating speed, polysilicon is used to draw the base electrode out of the element region to reduce the base area. Moreover, polysilicon resistors and metal wiring conductors are formed on the isolation oxide.
To reduce the base resistance r.sub.b, inactive base regions are made to have lower resistance and the emitter regions are made to have smaller width, thereby to reduce the resistance of the active base layer immediately under the emitter region. To improve the gain-bandwidth product f.sub.T, it is necessary to make shallow the junction of emitter and active base layers.
A prior art fabrication to produce a device having the above described features is shown in Japanese Patent Application Laid-open No. 19373/84 and will be described briefly with reference to FIGS. 1A through 1G.
FIG. 1A shows a state in which an isolation oxide film 4 has been formed for inter-element isolation on a P.sup.- silicon substrate 1, and an N.sup.+ collector sink region 5 for reducing the collector resistance has been formed. FIG. 1A also shows an N.sup.+ buried layer 2 and an N.sup.- epitaxial layer 3.
Then, as shown in FIG. 1B, a heavy boron compound, e.g., BF.sub.2.sup.+ is ion-implanted on the surface of the epitaxial layer 3 to form an active base layer 6.sub.1, and a polysilicon layer 7 and an oxidation-resistant film 8 comprising a silicon nitride film on a thin silicon oxide film are formed.
Subsequently, as shown in FIG. 1C, resist layers 80.sub.1, 80.sub.2, 80.sub.3 and 80.sub.4 are used for an etching to leave necessary parts of the oxidation-resistant film 8.sub.1, 8.sub.2, 8.sub.3 and 8.sub.4. The resist layers 80.sub.1, 80.sub.2, 80.sub.3, and 80.sub.4 and the oxidation-resistant films 8.sub.1, 8.sub.2, 8.sub.3 and 8.sub.4 serve as a mask in a subsequent boron ion implantation by which a high concentration base region 6.sub.2 is formed in part of the active base region.
Next, the resist layers 80.sub.1 to 80.sub.4 are removed, and an annealing is conducted. Then, as shown in FIG. 1D, polysilicon layer 7 is selectively oxidized by high pressure oxidation to form oxide films 9 isolating the polysilicon layers 7.sub.1, 7.sub.2 and 7.sub.3 to become electrodes of the transistor and the polysilicon layer 7.sub.4 to become a resistor.
The oxidation-resistant films 8.sub.1 through 8.sub.4 are then removed, and the surfaces of the polysilicon layers 7.sub.1 through 7.sub.4 are oxidized to form thin oxide. Then, as shown in FIG. 1E, arsenic is ion-implanted to a high concentration in the polysilicon layers 7.sub.2 and 7.sub.3 using resist layers 80.sub.5, 80.sub.6 and 80.sub.7 as a mask.
To introduce arsenic having a short projected range sufficiently into the polysilicon layers 7.sub.2 and 7.sub.3, excessive etching is necessary at the time of removing the silicon oxide film or the lower layer of the oxidation resistant film for removing bird's beaks which are formed at the time of the selective oxidation, and extend from the periphery towards the center of the polysilicon patterns.
The resist layers 80.sub.5 through 80.sub.7 are removed and then oxidation is conducted at a relatively low temperature to grow an oxide film. As shown in FIG. 1F, the resultant oxide film is thicker on the polysilicon layers 7.sub.2 and 7.sub.3 containing arsenic at a high concentration, than on the polysilicon layers 7.sub.1 and 7.sub.4. Utilizing this difference in thickness for self alignment, boron is ion-implanted in the polysilicon layers 7.sub.1 and 7.sub.4 to a high concentration, and heat treatment is conducted to form a low-resistance inactive base 10 and emitter 11.
After that, as shown in FIG. 1G, contact holes are opened and metal electrodes 12.sub.1, 12.sub.2, 12.sub.3, 12.sub.4 and 12.sub.5 are formed. By virtue of the thick oxide films surrounding the polysilicon patterns, the contact holes can be formed by self-alignment to have larger dimensions than the corresponding polysilicon electrodes.
Both ends of the emitter 11 in the direction normal to the page of the drawing have a walled emitter structure, in which the emitter 11 bounds on the isolation oxide film 4.
By the above-described process, transistors with the walled-emitter configuration can be easily fabricated. Moreover, since the base electrode is drawn out of the element region by means of polysilicon 7.sub.1, the base area is substantially reduced and the collector-base junction capacitance is reduced.
In addition, the inactive base 10 and, the high-concentration base region 6.sub.2 both have low resistance, so that the base resistance r.sub.b is also reduced.
The above-described process have the following problems: First, the base junction in the completed device, i.e., after the emitter formation, becomes about 0.4 micrometers even if the active base 6.sub.1, is initially formed in the shallow region by use of ion-implantation of a heavy compound such as BF.sub.2.sup.+. This is because, during the selective oxidation of polysilicon, the diffusion proceeds. It is therefore difficult to make the gain-bandwidth product f.sub.T be 5 GHz or more.
Secondly, at the time of removing the oxidation-resistant films 8.sub.1 to 8.sub.4, the silicon oxide film 9 must be excessively etched, as described above. As a result, when the contact hole is opened, the part of the base adjacent the emitter may be exposed, and consequently the exposed base and the emitter may be shorted by the metal electrode.
Thirdly, variation or fluctuation in various conditions during the active base formation and the emitter formation, e.g., the thickness of polysilicon layer, the width of the emitter, temperature distribution during the selective oxidation, effects the depth of the active base and the emitter. For this reason, the characteristics of the transistor, particularly the current amplification factor h.sub.FE differs from one place to another on the same wafer and from one wafer to another, and the reproducibility between production lots is poor.